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f o r p o w e r m a n a g e m e n t a p p l i c a t i o n c o n t r o l i n t e g r a t e d p o w e r s y s t e m ( c i p o s ? ) ig cm 10 f60 g a http://www. lspst. com d a t a s h e e t , aug. 20 10
cipos? igcm 10 f60ga data sheet 2 / 14 aug. 2010 revision history: 2010 - 08 ver . 1.1 previous version: datasheet ver. 1.0 page subjects (major changes since last revision) 11 t fltclr authors: junho song, junbae lee an d daewoong chung edition 20 10 - 0 7 published by ls power semitech co., ltd. seoul , korea ? the information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding t he application of the device, ls power semitech co., ltd. hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non - infringement of intellectual property rights of any third party. information for f urther information on technology, delivery terms and conditions and prices please contact your nearest ls power semitech co., ltd. o ffice or representatives ( http://www. lspst .com ). warnings due to technical requirements components may contain dangerous sub stances. for information on the types in question please contact your nearest ls power semitech co., ltd. o ffice or representatives. ls power semitech co., ltd. c omponents may only be used in life - support devices or systems with the express written approva l ls power semitech co., ltd. , if a failure of such components can reasonably be expected to cause the failure of that life - support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are int ended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
cipos? igcm 10 f60ga data sh eet 3 / 14 aug. 2010 table of c ontents cipo s? c ontrol i ntegrated p o wer system ................................ ................................ ................................ .. 4 features ................................ ................................ ................................ ................................ ........................ 4 target applications ................................ ................................ ................................ ................................ ..... 4 description ................................ ................................ ................................ ................................ ................... 4 system configuration ................................ ................................ ................................ ................................ . 4 pin configuration ................................ ................................ ................................ ................................ .............. 5 internal electrical schematic ................................ ................................ ................................ ........................... 5 pin assignment ................................ ................................ ................................ ................................ ................. 6 pin description ................................ ................................ ................................ ................................ ............ 6 hin (u,v,w) and lin (u,v,w) (low side and high si de control pins, pin 7 - 12 ) ................................ .......... 6 vfo ( fault - output and ntc , pin 1 4) ................................ ................................ ................................ ........... 7 itrip (over current detection function, pin 15 ) ................................ ................................ .......................... 7 vdd, vss ( low side control supply and reference, pin 13 , 16 ) ................................ ................................ .. 7 vb (u , v , w) and vs (u , v , w) (high side supplies, pin 1 , 2 , 3 , 4 , 5 , 6 ) ................................ .......................... 7 n u, n v, n w ( l ow side emitter, pin 17 , 18 , 19 ) ................................ ................................ .......................... 7 p ( p ositive bus input voltage, pin 23 ) ................................ ................................ ................................ .......... 7 absolute maximum ratings ................................ ................................ ................................ ............................. 8 module section ................................ ................................ ................................ ................................ ............ 8 rc - igbt section ................................ ................................ ................................ ................................ .......... 8 control section ................................ ................................ ................................ ................................ ............ 8 recommended operati on conditions ................................ ................................ ................................ ............ 9 static parameters ................................ ................................ ................................ ................................ ............ 10 dynamic parameters ................................ ................................ ................................ ................................ ...... 11 bootstrap parameters ................................ ................................ ................................ ................................ .... 11 thermistor ................................ ................................ ................................ ................................ ...................... 12 mechanic al characteristics and ratings ................................ ................................ ................................ ...... 12 circuit of a typical application ................................ ................................ ................................ ..................... 13 switching times definition ................................ ................................ ................................ ............................ 13 package outline ................................ ................................ ................................ ................................ .............. 14
cipos? igcm 10 f60ga data sheet 4 / 14 aug. 2010 cipos? c o ntrol i n tegrated p o wer s ystem dual in - line intelligent power module 3 - bridge 600v / 10 a features fully isolated dual in - line molded module ? infineon reverse conducting igbts with monolithic body diode ? rugged soi gate driver technology with st ability against transient and negative voltage ? allowable negative vs potential up to - 11v for signal transmission at vbs=15v ? integrated bootstrap functionality ? over current shutdown ? temperature monitor ? under - voltage lockout at all channels ? low side emitte r pins accessible for all phase current monitoring (open emitter) ? cross - conduction prevention ? all of 6 switches turn off during protection ? minimum deadtime built in driver ic ? l ead - free terminal plating; rohs compliant target applications ? dish washer s ? re frigerator s ? washing machines ? air - conditioners ? fans ? low power motor drives description the cipos? module family offers the chance for integrating various power and control components to increase reliability, optimize pcb size and system costs . it is designed to control three phase ac motors and permanent magnet motors in variable speed drives for applications like air conditioning, refrigerator and washing machine. the package concept is specially adapted to power applications, which need good ther mal conduction and electrical isolation, but also emi - save control and overload protection. the features of infineon reverse conducting igbt are combined with a n optimized soi gate driver for excellent electrical performance. system configuration ? 3 half bridges with r everse c onducting igbt ? 3 soi gate driver ? thermistor ? pin - to - heasink c reepage distance typ . 1. 6 mm
cipos? IGCM10F60GA data sheet 5 / 14 aug. 2010 pin configuration bottom view figure 1 : pin configuration internal ele ctrical schematic figure 2 : internal s chematic ( 1 ) v s ( u ) ( 2 ) v b ( u ) ( 3 ) v s ( v ) ( 4 ) v b ( v ) ( 5 ) v s ( w ) ( 6 ) v b ( w ) ( 7 ) h i n ( u ) ( 8 ) h i n ( v ) ( 9 ) h i n ( w ) ( 1 0 ) l i n ( u ) ( 1 1 ) l i n ( v ) ( 1 2 ) l i n ( w ) ( 1 3 ) v d d ( 1 4 ) v f o ( 1 5 ) i t r i p ( 1 6 ) v s s ( 2 3 ) p ( 2 2 ) u ( 2 1 ) v ( 2 0 ) w ( 1 9 ) n u ( 1 8 ) n v ( 1 7 ) n w ( 2 4 ) n c v s s v d d l i n 3 l i n 2 l i n 1 v f o i t r i p l o 3 l o 2 l o 1 h o 1 h o 2 h o 3 v b 1 v s 1 v b 2 v s 2 v b 3 v s 3 h i n 3 h i n 2 h i n 1 n w ( 1 7 ) n v ( 1 8 ) w ( 2 0 ) v ( 2 1 ) u ( 2 2 ) p ( 2 3 ) ( 2 ) v b ( u ) ( 1 5 ) i t r i p ( 1 4 ) v f o ( 1 0 ) l i n ( u ) ( 1 1 ) l i n ( v ) ( 1 2 ) l i n ( w ) ( 1 6 ) v s s ( 1 3 ) v d d ( 4 ) v b ( v ) ( 6 ) v b ( w ) ( 7 ) h i n ( u ) ( 8 ) h i n ( v ) ( 9 ) h i n ( w ) ( 1 ) v s ( u ) ( 3 ) v s ( v ) ( 5 ) v s ( w ) n u ( 1 9 ) n c ( 2 4 ) t h e r m i s t o r r b s 1 r b s 2 r b s 3
cipos? IGCM10F60GA data sheet 6 / 14 aug. 2010 pin assignment pin number pin name pin description 1 vs(u) u - phase h igh side floating ic supply offset voltage 2 vb (u) u - phase h igh side floating ic su pply voltage 3 vs(v) v - phase h igh side floating ic supply offset voltage 4 vb (v) v - phase h igh side floating ic supply voltage 5 vs(w) w - phase h igh side floating ic supply offset voltage 6 vb (w) w - phase h igh side floating ic supply voltage 7 hin (u) u - p hase high side gate driver i nput 8 hin (v) v - phase high side gate driver i nput 9 hin (w) w - phase high side gate driver i nput 10 lin (u) u - phase low side gate driver i nput 11 lin (v) v - phase low side gate driver i nput 12 lin (w) w - phase low side gate dri ver i nput 13 vdd low side control supply 14 vfo fault output / temp e rature monitor 15 i trip o ver current shutdown input 16 vss low side control negative supply 17 nw w - phase l ow side emitter 18 nv v - phase low side emitter 19 n u u - phase low side e mitter 20 w motor w - phase output 21 v motor v - phase output 22 u motor u - phase output 23 p p ositive bus input voltage 24 nc no connection pin description hin (u,v,w) and lin (u,v,w) (low side and high side control pins, pin 7 - 12 ) these pins are pos itive logic and they are responsible for the control of the integrated igbt . the schmitt - trigger input threshold of them are such to guarantee lsttl and cmos compatibility down to 3.3v controller outputs. pull - down resistor of about 5 k ? is internally provided to pre - bias inputs during supply start - up and a zener clamp is provided for pin protection purposes. input schmitt - trigger and noise filter provide beneficial noise rejection to short input pulses . the noise filter suppresses contr ol pulses which are below the filter time t filin . the filter acts according to figur e 4 . figure 3 : input pin structure figur e 4 : input filter timing diagram u z = 1 0 . 5 v i n p u t n o i s e f i l t e r s c h m i t t - t r i g g e r s w i t c h l e v e l v i h ; v i l l i n x h i n x ? ? k 5 h i n l i n h o l o l o w h i g h t f i l i n t f i l i n a ) b ) h i n l i n h o l o
cipos? IGCM10F60GA data sheet 7 / 14 aug. 2010 it is recommended for proper work of cipos? not to provide input pulse - width lower than 1us. the integrated gate drive provides additionally a shoot through prevention capability which avoids the simultaneous on - state of two gate drivers of the same leg (i .e. ho1 and lo1, ho2 and lo2, ho3 and lo3). when two inputs of a same leg are activated, only former activated one is activated so that the leg is kept steadily in a safe state. a minimum deadtime insertion of typ 3 80 ns is also provided by driver ic , in or der to reduce cross - conduction of the external power switches. vfo ( fault - output and ntc , pin 1 4) the vfo pin indicates a module failure in case of under voltage at pin vdd or in case of triggered over current detection at itrip. a pull - up resistor is exte rnally required to bias the ntc. figure 5 : internal c ircuit at pin vfo the same pin provides direct access to the ntc, which is referenced to vss. an external pull - up resistor connected to +5v ensures , that the resulting voltage can be directly connected to the microcontroller itrip (over c urrent detection function, pin 1 5 ) c ipos? provides an over current detection function by connecting the itrip input with the motor current feedback. the itrip comparator threshold (typ 0.4 7 v) is referenced to vss ground. a input noise filter (typ: t itripmin = 53 0 ns ) prevents the driver to de tect false over - current events. ove r current detection generates a shut down of all outputs of the gate driver after the shutdown propagation delay of typically 1 0 0 0 ns. the fault - clear time is set to typical 6 5 u s . vdd , vss ( l ow side control supply and refe rence , pin 1 3 , 1 6 ) v dd is the low side supply and it provides power both to input logic and to low side output power stage. input logic is referenced to vss ground. the under - voltage circuit enables the device to operate at power on when a supply voltage o f at least a typical voltage of v dd uv+ = 12.1 v is present. the ic shuts down all the gate drivers power outputs, when the v dd supply voltage is below v dd uv - = 10. 4 v. this prevents the external power switches from critically low gate voltage levels during on - state and therefore from excessive power dissipation. vb (u , v , w) and vs (u , v , w) (high side supplies, pin 1 , 2 , 3 , 4 , 5 , 6 ) vb to vs is the high side supply voltage. the high side circuit can float with respect to vss following the external high side power device emitter voltage. due to the low power consumption, the floating driver stage is supplied by integrated bootstrap circuit. the u nder - voltage detection operates with a rising supply threshold of typical v bsuv+ = 12.1 v and a falling threshold of v dd u v - = 10. 4 v . vs (u,v,w) provide a high robustness against negative v oltage in respect of vss of - 50 v transiently . this ensures very stable designs even under rough conditions. n u, n v, n w ( l ow side emitter, pin 1 7 , 1 8 , 1 9 ) the l ow side emitters are available for current measurements of each phase leg. it is recommended to keep the connection to pin vss as short as possible in order to avoid unnecessary inductive voltage drops. p ( p ositive bus input voltage, pin 2 3 ) the high side igbt are connected to the bus voltage. it is recommended that the bus voltage does not exceed 4 00 v. vfo cipos? vss > 1 from uv - detection v dd r on , flt from itrip - latch thermistor
cipos? IGCM10F60GA data sheet 8 / 14 aug. 2010 absolute maximum ratings ( v dd = 15v and t c = 25c, if not stated otherwise ) module section description condition symbol value unit min max storage temperature range t stg - 40 125 c insulation test voltage rms, f= 6 0hz, t =1min v isol 2 0 00 - v operating case temperature range refer to figure 6 t c - 4 0 1 00 c rc - igbt section description condition symbol value unit min max max. blocking voltage i c =250 a v ces 600 - v o utput c urrent t c = 25 c , t j <150 c t c = 100 c , t j <150 c i c - 10 - 6 10 6 a maximum peak output current less than 1ms i c - 20 20 a short circuit withstand time v dc ? 400v t sc - 5 s power dissipation per igbt p tot - 26 w operating junction temperature range t j - 40 150 c single igbt thermal resistance, junction - case r thjc - 4.79 k/w control section description condition symbol value unit min max module supply voltage v dd - 1 20 v high side floating supply voltage (vb vs. vs) v bs - 1 20 v input voltage lin, hin, itrip v in v itrip - 1 - 1 10 10 v s witching frequency f pwm - 20 khz
cipos? IGCM10F60GA data sheet 9 / 14 aug. 2010 recommended operation conditions all voltages are a bsolute voltages referenced to v ss - p otential unless otherwise specified. description symbol value unit min typ max dc link supply voltage v dc 0 - 40 0 v high side floating supply voltage (v b vs. v s ) v bs 13.5 - 1 8 .5 v low side supply voltage v dd 14.0 16 1 8 .5 v control supply variation bs , dd - 1 - 1 - 1 1 v / s logic input voltages lin,hin,itrip v in v itrip 0 0 - 5 5 v between vss - n (including surge) v ss - 5 - 5 v figure 6 : t c measurement po int
cipos? IGCM10F60GA data sheet 10 / 14 aug. 2010 static parameters ( v dd = 15v and t c = 25c, if not stated otherwise) description condition symb ol value unit min typ max collector - emitter saturation voltage i out = 6 a t j = 25c 150c v ce(sat) - - 1. 6 1. 8 2. 0 - v emitter - collector forward voltage i out = - 6 a t j = 25c 150c v f - - 1. 7 5 1. 8 2. 2 v collector - emitter l eakage current v ce = 60 0v i ce s - - 1 m a logic " 1 " input voltage (lin,hin) v i h - 2.1 2. 5 v logic " 0 " input voltage (lin,hin) v il 0.7 0. 9 - v itrip positive going threshold v it,th+ 400 4 7 0 540 mv itrip input hysteresis v it,hys 40 70 - mv v dd and v bs supply under voltage positive going threshold v dduv+ v bsuv+ 10.8 12. 1 13.0 v v dd and v bs supply under voltage negative going thresho ld v dduv - v bsuv - 9.5 10. 4 11. 2 v v dd and v bs supply under voltage lockout hysteresis v dduvh v bsuvh 1 .0 1. 7 - v input clamp voltage (hin, lin, itrip) iin=4ma v inclam p 9.0 10. 1 12.5 v quiescent vb x supply current (vb x only) h i n = 0v i qb s - 3 0 0 500 a quiescent v dd supply current (vdd only) l i n = 0v , h inx =5v i qdd - 37 0 9 00 a input bias current v in = 5v i in+ - 1 1.5 m a input bias current v in = 0v i in - - 2 - a itrip i nput bias current v itrip = 5v i itrip+ - 65 1 5 0 a vfo input bias current vfo = 5v, v itrip = 0 v i fo - 6 0 - a vfo output voltage i fo = 10ma, v itrip = 1 v v fo - 0.5 - v
cipos? IGCM10F60GA data sheet 11 / 14 aug. 2010 dynamic parameters ( v dd = 15v and t c = 25c, if not stated otherwise) description condition symbol value unit min typ max turn - on propagation delay v lin,hi n = 5 v; i out = 6 a , v dc = 300v t d(on) - 650 - ns turn - on rise time v lin,hin = 5v ; i out = 6 a , v dc = 300v t r - 20 - ns turn - off propagation delay v lin,hin = 0 v; i out = 6 a , v dc = 300v t d(off) - 650 - ns turn - o ff fall time v lin,hin = 0v ; i out = 6 a , v dc = 300 v t f - 170 - ns short circuit propagation delay from v it,th+ to 1 0% i sc t scp - 125 0 - ns input filter time itrip v itrip = 1v t itripmin - 530 - ns input filter time at lin , hin for turn on and off v lin,hin = 0 v & 5v t filin - 2 9 0 - ns fault clear time after itrip - fault v itrip = 1 v t fltclr 40 6 5 1 3 0 s d eadtime between low side and high side dt pwm 1.5 - - s deadtime of gate drive circuit dt ic 380 ns igbt t urn - on e nergy (includes reverse recovery of diode) v dc = 300v , i c = 6 a, t j = 25c 150c e on - - 110 155 - - j igbt t urn - o ff e nergy v dc = 300v , i c = 6 a, t j = 25c 150c e off - - 155 220 - - j diode recovery e nergy v dc = 300v , i c = 6 a, t j = 25c 15 0c e rec - - 45 75 - - j bootstrap parameters (t c = 25c, if not stated otherwise) description condition symbol value unit min typ max repetitive peak reverse voltage v rrm 600 v bootstrap resistance of u - phase 1 vs2 or vs3= 300v, t j =25c vs2 and vs3=0v, t j =25c vs2 or vs3=300v, t j = 1 25c vs2 and vs3=0v, t j = 1 25c r bs1 35 40 50 65 ? f =0.6a, di/dt=80a/ s t r r _bs 50 ns forward voltage drop i f =20ma, vs2 and vs3=0v v f_bs 2.6 v 1 r bs2 and r bs3 have same values to r bs1 .
cipos? IGCM10F60GA data sheet 12 / 14 aug. 2010 thermistor description condition symbol value unit min typ max resistor t ntc = 25 c r ntc - 85 - k ? b - constant of ntc (negative temperature coefficient) b(25/100) - 4092 - k mechanical characteristics and ratings description condition value unit min t yp max mounting torque m3 screw and washer 0.59 0.69 0.78 nm flatness refer to figure 7 - 50 - 100 m weight - 6.15 - g figure 7 : flatness measurement position + + - -
cipos? IGCM10F60GA data sheet 13 / 14 aug. 2010 circuit of a typical application figure 8 : application circuit switching times definiti on figure 9 : switching times definition 3 - p h a c m o t o r m i c r o c o n t r o l l e r v d d l i n e 5 o r 3 . 3 v l i n e s i g n a l f o r s h o r t - c i r c u i t p r o t e c t i o n u - p h a s e c u r r e n t s e n s i n g v - p h a s e c u r r e n t s e n s i n g w - p h a s e c u r r e n t s e n s i n g u v s s v d d l i n 3 l i n 2 l i n 1 v f o i t r i p l o 3 l o 2 l o 1 h o 1 h o 2 h o 3 v b 1 v s 1 v b 2 v s 2 v b 3 v s 3 h i n 3 h i n 2 h i n 1 n w ( 1 7 ) n v ( 1 8 ) w ( 2 0 ) v ( 2 1 ) u ( 2 2 ) p ( 2 3 ) ( 2 ) v b ( u ) ( 1 5 ) i t r i p ( 1 4 ) v f o ( 1 0 ) l i n ( u ) ( 1 1 ) l i n ( v ) ( 1 2 ) l i n ( w ) ( 1 6 ) v s s ( 1 3 ) v d d ( 4 ) v b ( v ) ( 6 ) v b ( w ) ( 7 ) h i n ( u ) ( 8 ) h i n ( v ) ( 9 ) h i n ( w ) ( 1 ) v s ( u ) ( 3 ) v s ( v ) ( 5 ) v s ( w ) n u ( 1 9 ) n c ( 2 4 ) t h e r m i s t o r r b s 1 r b s 2 r b s 3 h i n l i n i c u , i c v , i c w v c e u , v c e v , v c e w 0 . 9 v 2 . 1 v 9 0 % 1 0 % 1 0 % 1 0 % 9 0 % t d ( o f f ) t f t d ( o n ) t r
cipos? IGCM10F60GA data sheet 14 / 14 aug. 2010 package outline

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